SmartDV’s MIPI SPP TS IP is a silicon-proven, fully featured SneakPeek Protocol Target System solution purpose-built for SoC designs requiring standards-compliant, on-chip debug access without a dedicated debug port. Fully compliant with MIPI SPP v2.2, it implements the complete target-side SneakPeek command engine, receiving Command Packets grouped into SneakPeek Transfer Blocks (SPTBs), executing the requested transactions against the target’s address space, and returning Response Packets — replacing dedicated debug interfaces such as JTAG with familiar address-mapped read and write transactions.
Designed to give SoC teams a comprehensive, production-tested debug access solution, the IP supports all three v2.2 Agent types — Memory Agents for address-mapped resource access, JTAG Agents for debug and scan via TAP, and Fabric Agents for discrete message send and receive to system fabric endpoints. Its support for both FullSPP and TinySPP packet structures, optional extended mode for asymmetric WriteReadSystem payloads, and Secure Communication Manager Access Space via SPDM-based authentication and encryption makes it a future-ready, spec-complete target-side implementation suited for production field debug environments.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, shared-network-friendly design, and clean system interconnect interface enable fast integration and confident design bring-up across a wide range of process nodes and target SoC applications.
