SmartDV’s JESD204D Transmitter IP is a fully featured next-generation serial interface transmitter solution purpose-built for SoC designs requiring the highest available data converter interface bandwidth across 5G/6G wireless infrastructure, phased array radar, aerospace, defense, and medical imaging applications. Fully compliant with JESD204D (released December 2023), it delivers complete transmitter functionality supporting data rates up to 116 Gbps with PAM4 signaling and up to 58 Gbps with NRZ (PAM2) signaling, doubling the per-lane bandwidth of JESD204C.1 while maintaining full backward compatibility with JESD204B and JESD204C.1 link layers.
Designed to address the extreme bandwidth demands of next-generation RF sampling and data converter systems, the IP supports 1 to 8 lanes with 1 to 64 converters per transmitter, 1 to 8 samples per converter, Sub-class 0, 1, and 3, and a new alignment scheme for FEC, frame, and lane synchronization. Its Reed-Solomon Forward Error Correction implementation across five RS-FEC modes based on IEEE 802.3 Clause 91 — including FEC1 (136,130), FEC2 (144,130), FEC3 (272,258), FEC4 (544,514), and FEC5 (528,514) — gives RF and instrumentation SoC teams a production-ready JESD204D transmitter implementation for the most demanding next-generation high-speed data converter interfaces.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane and converter architecture and clean host interface enable fast integration across a wide range of RF and data converter process nodes.
