SmartDV’s JESD204 Cyclic FEC IP is a silicon-proven, fully featured Forward Error Correction solution purpose-built for SoC designs requiring reliable, standards-compliant error correction for high-speed serial links between data converters and logic devices. Fully compliant with JESD204C.1 FEC functionality, it implements the (2074, 2048) binary cyclic code, shortened from the cyclic Fire code (8687, 8661), with 26 parity bits providing robust link budget improvement for instrumentation and test and measurement applications operating at the most demanding lane rates.
Designed to address the burst-error characteristics of high-speed data converter serial links, the IP corrects burst errors up to 9 bits within each 2048-bit scrambled data multiblock, using a pipelined error correction mechanism for efficient, low-latency FEC processing. Its minimum latency of 58 blocks for detection and correction of a bit error in the first scrambled data bit of a multiblock gives RF, instrumentation, and data converter SoC teams a production-tested, spec-complete FEC implementation available as an optional feature alongside the 64b/66b and 64b/80b link layer encoding schemes.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration across a wide range of data converter and RF process nodes.
