SmartDV’s Ethernet 25G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring reliable, single-lane 25 Gigabit Ethernet connectivity across data center, enterprise networking, and high-performance computing applications. Fully compliant with IEEE 802.3-2022 Clause 107, it delivers complete 25GBASE-R and 25GBASE-KR PCS functionality with 64b/66b encoding and decoding, providing a cost-effective single-lane alternative to legacy multi-lane 100G interconnects derived from proven 25 Gbps-per-lane technology.
Designed to address the demanding signal integrity requirements of modern single-lane data center interconnects, the IP implements complete 64b/66b encoding and decoding for both transmit and receive paths, data scrambling and descrambling, gearbox functionality for XSBI data width conversion, block synchronization, bit error rate monitoring, and RS-FEC per IEEE 802.3-2022 Clause 108 with dedicated error correction and error detection capability for demanding backplane and copper cable channels. Its loopback functionality, receiver link fault status detection, and IEEE 802.3az Energy Efficient Ethernet support give data center SoC teams a production-tested, spec-complete 25G PCS implementation for cost-effective single-lane network interconnect designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized PCS to SerDes interface architecture and clean host interface enable fast integration across a wide range of data center process nodes.
