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Overview

SmartDV’s Ethernet TSN MAC IP is a silicon-proven, fully featured Time-Sensitive Networking Media Access Controller solution purpose-built for SoC designs requiring deterministic, low-latency Ethernet across automotive zonal architecture, industrial automation, and professional audio/video applications. Fully compliant with IEEE 802.3-2022 and the core TSN standard suite, it delivers speed-independent TSN MAC functionality applicable across 10 Mbps through multi-gigabit Ethernet rates, giving SoC teams a single deterministic MAC architecture that scales across the full range of TSN-enabled network speeds rather than being tied to a single physical layer rate.

Designed to address the demanding determinism and reliability requirements of modern time-sensitive networks, the IP implements IEEE 802.1Qbu frame preemption together with IEEE 802.3br Interspersing Express Traffic, IEEE 802.1AS-2025 (gPTP) and IEEE 1588-2008 (PTP) timing synchronization, IEEE 802.1Qbv scheduled traffic shaping and IEEE 802.1Qav credit-based shaping, IEEE 802.1Q class-based flow control with 8 traffic classes, and IEEE 802.1CB frame replication and elimination for reliability. Its full and half duplex support, VLAN frame handling, cut-through switching, and independently enable/disable TSN feature architecture give automotive and industrial SoC teams a production-tested, spec-complete TSN MAC implementation adaptable to any underlying Ethernet PHY speed.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its ultra-low latency, compact implementation and clean host interface enable fast integration across a wide range of automotive and industrial process nodes.

Ethernet 10M/100M/1G TSN MAC
Key Features
  • Full TSN MAC Functionality – Complete Time-Sensitive Networking MAC implementation compliant with IEEE 802.3-2022, architecturally speed-independent and adaptable across 10 Mbps through multi-gigabit Ethernet rates
  • Frame Preemption – IEEE 802.1Qbu and IEEE 802.3br Interspersing Express Traffic for low-latency delivery of critical frames alongside best-effort traffic
  • Precision Time Synchronization – IEEE 802.1AS-2025 (gPTP) and IEEE 1588-2008 (PTP) timing synchronization for network-wide deterministic scheduling
  • Traffic Scheduling and Shaping – IEEE 802.1Qbv scheduled traffic (time-aware shaper) and IEEE 802.1Qav credit-based shaping for bounded-latency traffic classes
  • Frame Replication and Elimination – IEEE 802.1CB frame replication and elimination for high-reliability, redundant-path network designs
  • Class-Based Flow Control – IEEE 802.1Q class-based FIFO with support for 8 traffic classes for deterministic QoS management
  • Independently Configurable TSN Features – Each TSN feature individually enabled or disabled for application-specific deterministic network profiles
  • Ultra-Low Latency Cut-Through – Cut-through switching support for minimal frame delivery latency in time-critical applications
  • Flexible Physical Interface – GMII, RGMII, and MII interface support with programmable IPG, preamble length, and configurable TX/RX FIFOs
  • VLAN Frame Support – Complete VLAN frame handling for network segmentation in TSN-enabled topologies
  • Full and Half Duplex Operation – Support for both full-duplex and half-duplex modes for broad TSN deployment flexibility
  • Comprehensive Statistics Gathering – Detailed statistics collection for network diagnostics and TSN schedule validation
Compliance and Compatibility
  • Fully compliant with IEEE 802.3-2022
  • Compliant with IEEE 802.1Qbu, IEEE 802.3br, IEEE 802.1AS-2025, IEEE 1588-2008, IEEE 802.1Qbv, IEEE 802.1Qav, IEEE 802.1Q, and IEEE 802.1CB
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows