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Overview

SmartDV’s Ethernet Tri-Speed MAC IP is a silicon-proven, fully featured Media Access Controller solution purpose-built for SoC designs requiring flexible, multi-speed Ethernet connectivity across networking, embedded, and industrial applications. Fully compliant with IEEE 802.3-2022, it delivers complete MAC functionality across 10 Mbps, 100 Mbps, and 1 Gbps operation with both full-duplex and half-duplex mode support, GMII and MII interfaces, and comprehensive statistics gathering for network diagnostics.

Designed for the practical integration requirements of modern multi-speed networking SoC designs, the IP supports programmable Inter Packet Gap and preamble length, IEEE 802.3az Energy Efficient Ethernet, IEEE 802.1Q and 802.1ad VLAN tagging, Wake-on-LAN, control frame and jumbo frame handling, FCS generation and checking, and Pause frame-based flow control in full-duplex mode. Its transmit and receive FIFO interface architecture gives networking SoC teams a production-tested, spec-complete Tri-Speed MAC implementation suited for flexible port speed configuration across enterprise, industrial, and embedded networking designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized speed mode architecture and clean host interface enable fast integration across a wide range of networking and embedded process nodes.

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Ethernet 10M/100M/1G MAC
Key Features
  • Full Tri-Speed MAC Functionality – Complete MAC implementation per IEEE 802.3-2022 supporting 10 Mbps, 100 Mbps, and 1 Gbps operation with full-duplex and half-duplex modes
  • Flexible Physical Interface – GMII and MII interface support for broad PHY compatibility across all supported speeds
  • VLAN Tag Support – IEEE 802.1Q and IEEE 802.1ad VLAN tagging for standards-compliant network segmentation
  • Energy Efficient Ethernet Support – IEEE 802.3az EEE support for power-efficient operation during periods of low link utilization
  • Wake-on-LAN Support – Complete Wake-on-LAN functionality for remote system power management
  • Control and Jumbo Frame Handling – Complete control frame and jumbo frame support for extended payload networking applications
  • FCS Generation and Checking – Complete Frame Check Sequence (CRC) generation on transmit and checking on receive for data integrity
  • Pause Frame Flow Control – Pause frame-based flow control in full-duplex mode for congestion management
  • Programmable Frame Timing – Programmable Inter Packet Gap (IPG) and preamble length for flexible protocol timing configuration
  • Comprehensive Statistics Gathering – Detailed per-port statistics collection as per specification for network diagnostics and monitoring
  • Transmit and Receive FIFO Interface – Configurable transmit and receive FIFO architecture for efficient data buffering across all supported speeds
Compliance and Compatibility
  • Fully compliant with IEEE 802.3-2022 standard specifications
  • Compliant with IEEE 802.3az Energy Efficient Ethernet
  • Compliant with IEEE 802.1Q and IEEE 802.1ad VLAN tagging
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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