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eSPI Slave to LPC Bridge IP
Design IP
Overview

SmartDV’s eSPI Slave to LPC Bridge IP is a silicon-proven solution that enables seamless interoperability between next-generation systems using eSPI (Enhanced Serial Peripheral Interface) and legacy devices operating on the LPC (Low Pin Count) interface. Fully compatible with Intel’s eSPI and LPC specifications, this bridge IP facilitates smooth system migration by preserving access to LPC-based peripherals in modern embedded, automotive, and industrial applications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It supports key eSPI command sets, including I/O, memory, and message cycles, along with power management features such as out-of-band (OOB) signaling and virtual wire communication. The bridge also handles serialization/deserialization and timing management, ensuring reliable, low-latency performance.

eSPI Slave to LPC Bridge
Benefits
  • Seamless Legacy Bridging – Converts eSPI Peripheral Channel transactions into equivalent LPC memory or I/O read/write operations, enabling backward compatibility with legacy devices
  • Full LPC Host Capability – Supports LPC master interface with I/O read/write and memory read/write frames as defined in LPC specification
  • Robust Interrupt and Wait-State Support – Implements Serial IRQ interface and allows variable wait-states to meet system timing requirements
  • Flexible System Integration – Supports both Single Master–Single Slave and Single Master–Multiple Slave topologies
  • Multi-Channel Bridging – Bridges eSPI Peripheral Channel to LPC with full support for transaction framing and timing
  • Optimized Throughput and Low Latency – Designed to minimize conversion overhead between eSPI and LPC domains
  • Reset and Timing Aware – Accurately propagates reset events between eSPI and LPC interfaces and maintains timing protocol compliance
Compliance and Compatibility
  • Compliant with LPC Interface Specification Version 1.1 and eSPI Specification Revision 1.5
  • Compatible with all major EDA synthesis, simulation, and linting flows