SmartDV’s DDR3/3L Controller IP is a silicon-proven, fully featured DRAM memory controller solution purpose-built for SoC designs requiring high-performance DDR3 and DDR3L memory connectivity across embedded, automotive, networking, and industrial applications. Supporting both DDR3 per JESD79-3F with DFI v2.0 and DDR3L per 8GB_DDR3L with DFI v3.1, it delivers complete controller functionality supporting up to 8 GB device density, up to 16 AXI ports with data widths up to 512 bits, all speed grades, and X4, X8, and X16 device types.
Designed to maximize memory performance in demanding SoC designs, the IP supports configurable open and closed page policies, low-latency write and read paths, transaction reordering for higher performance, in-port and multi-port AXI arbitration, burst lengths of 4 and 8 in both Sequential and Interleave types, Write Data Mask, Power Down features, DLL, Write Leveling, ZQ/Output Driver Calibration, auto and manual self-refresh, Self Refresh Temperature, Multipurpose Register, Nominal and dynamic On-Die Termination, and Partial Array Self Refresh. Its controllable outstanding transactions per AXI write and read channel and high clock speed support for both ASIC and FPGA give memory subsystem teams a production-tested, spec-complete DDR3/3L controller.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized AXI port count and configurable page policy enable fast integration across a wide range of process nodes.
