SmartDV’s DDR4 Controller IP is a silicon-proven, fully featured DDR4 DRAM memory controller solution purpose-built for SoC designs requiring high-performance, high-capacity memory connectivity across AI/ML, automotive, high-performance computing, and data center applications. Supporting JEDEC DDR4 specifications JESD79-4 through JESD79-4D and compliant with DFI v3.0 or higher, it delivers complete controller functionality supporting up to 16 GB device density, up to 16 AXI ports with data widths up to 512 bits, all speed grades, and X4, X8, X16, and X32 device types.
Designed to maximize DDR4 memory performance in demanding SoC designs, the IP supports configurable open and closed page policies, transaction reordering, in-port QoS-based arbitration and multi-port arbitration, programmable burst lengths of 4 and 8 in Sequential and Interleave types, Write Data Mask and Data Bus Inversion, CRC write and read operations, Command Address Parity, Fine Granularity Refresh Mode, DQ Vref training, Write Leveling, ZQ Calibration, Read Preamble training, Programmable Preamble, Power Down and Maximum Power Saving Mode, DLL, Gear Down mode, CAL Mode, and Post Package Repair. Its 1:4 Controller to DFI PHY frequency ratio, built-in self-test, and Connectivity Test mode give memory subsystem teams a production-tested, spec-complete DDR4 controller.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized AXI port count and clean host interface enable fast integration across a wide range of advanced process nodes.
