DDR5 (DIMM + NVRAM + DFI) VIP

Simulation

Key Features Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s DDR5 Verification IP is a comprehensive solution for verifying DDR5 SDRAM memory interfaces across device, non-volatile RAM, DIMM module, and PHY interface implementations. Fully compliant with JEDEC JESD79-5 through JESD79-5D for DDR5 devices, the DDR5 NVRAM extension specification, and DFI versions 2.0 through 5.0, it provides complete verification coverage across DDR5 standalone devices supporting densities up to 64 GB, DDR5 NVRAM devices supporting densities up to 1 TB, DDR5 RDIMM and LRDIMM module types, and the DDR PHY Interface across DDR3, DDR4, DDR5, LPDDR3, LPDDR4, and LPDDR5 memory protocols.

SmartDV’s DDR5 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive refresh management verification including ARFM, DRFM, and PASR, Per-Row Activation Counting, advanced Post Package Repair coverage including hard, soft, and MBIST PPR, complete training mode support, DFI multi-protocol coverage, bus-accurate timing for all timing delay ranges, built-in functional coverage, and a complete test suite, SmartDV’s DDR5 VIP enables verification teams to thoroughly validate DDR5 memory subsystem designs for server, AI, data center, networking, and high-performance computing applications.

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DDR5 (DIMM + NVRAM + DFI) VIP

Key Features

Complete DDR5 Device Protocol Coverage – Supports 100% of the DDR5 protocol standard across JESD79-5 through JESD79-5D, all DDR5 commands, x4, x8, and x16 device widths, densities up to 64 GB, all speed grades up to 8800 MT/s, programmable write and read latency, programmable preamble, postamble and interamble, programmable burst lengths of 8, 16, and 32, sequential burst type, and 2N mode.
Comprehensive DDR5 Device Feature Support – Covers all mode register programming, write data mask, CRC for write, read, and MRR operations, DLL, write leveling, CA, CS, and read preamble training, MIR and CAI operations, read training pattern, Vref CA, Vref CS, and Vref DQ training, ZQ calibration, write pattern command, auto precharge for write, read, and write pattern commands, multipurpose command, VrefCA and VrefCS commands, per DRAM addressability, connectivity test mode, loopback, target row refresh, precharge command modes, synchronous and asynchronous ODT, self refresh, power down, maximum power saving mode, and input clock stop and frequency change.
Advanced Refresh Management and Data Integrity – Supports Fine Granularity Refresh modes and global refresh counter, Refresh Management All command and Same Bank command, Adaptive Refresh Management (ARFM), Directed Refresh Management (DRFM), temperature compensated refresh reporting, Partial Array Self Refresh (PASR), Self Refresh Entry with frequency change (SREF), and Per-Row Activation Counting (PRAC) as introduced in JESD79-5C for wordline-level activation monitoring and data integrity management.
Comprehensive Post Package Repair Support – Covers hard Post Package Repair (hPPR), soft Post Package Repair (sPPR), Memory Built-In Self-Test Post Package Repair (mPPR), MBIST PPR, and sPPR undo and lock as per JESD79-5A and later revisions.
DDR5 NVRAM Support – Supports DDR5 NVRAM devices from all leading vendors across x4, x8, and x16 device widths with densities up to 1 TB, covering all DDR5 NVRAM commands, CA, CS, and read preamble training, write leveling, programmable burst lengths of 8, 16, and 32, all mode register programming, write data mask, CRC for write and read operations, ZQ calibration, per DRAM addressability, row extension command, multipurpose command, loopback, self refresh, power down, maximum power saving mode, Post Package Repair, connectivity test mode, and CA Vref and DQ Vref training.
DDR5 DIMM Module Support – Supports 100% of the DDR5 DIMM protocol standard across RDIMM and LRDIMM types with densities up to 64 GB, x4, x8, and x16 device widths, all DDR5 DRAM features, CA, CS, and read preamble training, MIR, CAI, and 2N mode operations, programmable burst lengths of 8, 16, and 32, write data mask and write pattern command, CRC for write, read, and MRR operations, refresh management, Post Package Repair, target row refresh, loopback, per DRAM addressability, precharge command modes, Vref CA, Vref CS, and Vref DQ training, ZQ calibration, ODT, connectivity test mode, and all timing delay ranges in one model.
Multi-Protocol DFI Interface Support – Compliant with DFI versions 2.0 through 5.0 supporting DDR3, DDR4, DDR5, LPDDR3, LPDDR4, and LPDDR5 memory protocols across all DFI interface groups, with 1:1, 1:2, and 1:4 MC to PHY frequency ratios, write transactions with DBI, DM, and CRC, read transactions with DBI, per-slice read leveling, CA training, DB data buffer training, DDR write DQ training, write leveling strobe update, PHY-independent training mode, gear down and 2N mode, 3D stack support, WCK control interface for LPDDR5, frequency change protocol, CA parity signaling, DRAM clock disabling, and bus-accurate timing for minimum, typical, and maximum values.
Comprehensive Protocol Checking and Monitoring – Provides continuous monitoring of DDR5 device, NVRAM, DIMM, and DFI behavior during simulation, covering power up, initialization, power off, state-based rules, active command rules, read and write command rules, and all timing violations, with protocol checkers fully compliant with JESD79-5 through JESD79-5D and DFI 2.0 through 5.0 specifications.

Compliance and Compatibility

Fully compliant with JEDEC JESD79-5 through JESD79-5D (DDR5 SDRAM)
Supports DDR5 NVRAM extension specification
Supports DDR5 RDIMM and LRDIMM module types
Compliant with DFI versions 2.0, 2.1, 3.0, 3.1, 4.0, and 5.0
DFI protocol support covers DDR3, DDR4, DDR5, LPDDR3, LPDDR4, and LPDDR5
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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