SmartDV’s DDR5 Controller IP is a silicon-proven, fully featured DDR5 DRAM memory controller solution purpose-built for SoC designs requiring next-generation, high-bandwidth memory connectivity across AI/ML accelerators, high-performance computing, and data center applications. Compliant with JEDEC DDR5 specification JESD79-5D and backward compatible with JESD79-5C, JESD79-5B, JESD79-5A, and JESD79-5, and compliant with DFI v5.0, it delivers complete controller functionality supporting up to 64 GB device density, up to 16 AXI ports with data widths up to 512 bits, all speed grades, and X4, X8, and X16 device types.
Designed to maximize DDR5 memory performance in the most demanding AI and data center SoC designs, the IP supports configurable open and closed page policies, transaction reordering, QoS-based in-port arbitration, programmable burst lengths of 8, 16, and 32 in Sequential burst type, comprehensive refresh management including Fine Granularity, Global, Same Bank, and Adaptive Refresh Management, Directed Refresh Management, Write Pattern Command, CA/CS/Read Preamble training, MIR and CAI operations, Write Leveling, ZQ Calibration, CRC, Post Package Repair including hard/soft/MBIST PPR, Target Row Refresh, 2N mode, Self Refresh and Power Down, MPSM, SREF with frequency change, Partial Array Self Refresh, Connectivity Test, and 1:4/1:2/1:1 Controller to DFI PHY frequency ratios.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized AXI port count and clean host interface enable fast integration across a wide range of advanced process nodes.
