SmartDV’s CPRI Synthesizable Transactor is a fully featured Common Public Radio Interface bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable CPRI transmit and receive behavior during pre-silicon validation of wireless fronthaul and baseband-to-radio link designs. Fully compliant with CPRI v7.1 and backward compatible with v6.1, v6.0, v5.0, and v4.2, it delivers complete CPRI Physical Link Layer (Layer 1) functionality across all standard line bit rates from 614.4 Mbps up to 24,330.24 Mbps, giving validation teams a drop-in synthesizable CPRI transactor ready for rapid integration into emulation and prototyping flows for both Radio Equipment Controller (REC) and Radio Equipment (RE) node validation.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It models complete CPRI Hyperframe framing with IQ data, sync, C&M data, and vendor-specific information interleaving, both slow C&M (serial HDLC) and fast C&M (serial Ethernet) sub-channel mapping, the hardware start-up sequence state machine for both REC and RE nodes, and full Link Maintenance including LOS/LOF detection, RAI, and SDI indication, enabling validation teams to exercise corner-case CPRI behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its bus-accurate timing, comprehensive line coding support, and rich set of configuration parameters controlling CPRI functionality enable rapid deployment for early software bring-up and system-level validation of CPRI-based fronthaul system designs.
