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Overview

SmartDV’s CPRI Verification IP is a comprehensive solution for verifying the Common Public Radio Interface, a high-speed serial fronthaul interface defining the link between Radio Equipment Controllers and Radio Equipment in mobile base station deployments. Fully compliant with CPRI Specification v7.0 and backward compatible with v6.1, v6.0, v5.0, and v4.2, it supports complete verification of CPRI TX and RX functionality across all eleven defined line bit rates from 614.4 Mbps to 24330.24 Mbps, 8B/10B line coding for rates up to 9830.4 Mbps, 64B/66B line coding with and without RS-FEC for higher rate operation, and all CPRI layer 1 features including Hyperframe framing, sub-channel mapping, synchronization, and link maintenance for both REC and RE nodes.

SmartDV’s CPRI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With configurable scrambler support, comprehensive error injection and detection across all CPRI error types, L1 Inband Protocol support, hardware startup sequence state machine for both REC and RE nodes, bus-accurate timing checks, built-in functional coverage, and a complete test suite, SmartDV’s CPRI VIP enables verification teams to thoroughly validate CPRI fronthaul interface designs for 4G LTE, 5G NR, C-RAN, and O-RAN radio base station applications.

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CPRI VIP
Benefits
  • Full CPRI TX/RX Node SupportProvides complete CPRI transmitter and receiver functionality for both Radio Equipment Controller and Radio Equipment nodes, with a hardware startup sequence state machine covering L1 synchronization, protocol setup, and C&M plane setup, and support for bus-accurate timing and timing checks.
  • Comprehensive Line Bit Rate Coverage – Supports all eleven CPRI line bit rates including 614.4, 1228.8, 2457.6, 3072.0, 4915.2, 6144.0, 8110.08, 9830.4, 10137.6, 12165.12, and 24330.24 Mbps, with 8B/10B line coding for rates up to 9830.4 Mbps and 64B/66B line coding for higher rate operation.
  • RS-FEC and Advanced Encoding Support – Supports 64B/66B line coding without RS-FEC for 8110.08, 10137.6, 12165.12, and 24330.24 Mbps, and 64B/66B with RS-FEC for 24330.24 Mbps covering all three RS-FEC configurations: with alignment marker without scrambler, without alignment marker with scrambler, and without alignment marker without scrambler.
  • Hyperframe Framing and Sub-Channel Mapping – Performs CPRI Hyperframe framing with interleaving of IQ data, synchronization, C&M data, and vendor-specific information, supporting 8-bit, 16-bit, and 32-bit IQ data widths, slow C&M channel via serial HDLC at all defined standard HDLC bit rates, fast C&M channel via serial Ethernet, and vendor-specific data merging via a parallel interface.
  • Synchronization, Link Maintenance, and L1 Inband Protocol – Supports synchronization and timing as per CPRI specification, L1 Inband Protocol, and complete link maintenance including LOS detection, LOF detection, RAI indication, and SDI indication.
  • Scrambler and Error Injection Support – Supports configurable scrambler with enable and disable control, scrambler error insertion, disparity error and invalid code insertion for 8B/10B, and glitch injection and detection for comprehensive physical layer verification.
  • Comprehensive Error Detection and Reporting – Detects and reports all CPRI error types including invalid control and data characters, scrambler errors, disparity errors, invalid 10-bit code group errors, undersize and oversize frames, CRC errors, framing errors, LOS and LOF errors, block sync bit errors, block encoding errors, RS-FEC alignment marker errors, and RS-FEC parity errors.
  • Complete Verification Infrastructure – Provides built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in Master, Slave, and Monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with CPRI Specification v7.0; backward compatible with v6.1, v6.0, v5.0, and v4.2
  • Supports 8B/10B and 64B/66B line coding with optional RS-FEC
  • Supports all eleven CPRI standard line bit rates from 614.4 Mbps to 24330.24 Mbps
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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