SmartDV’s AVSBus 2.0 Verification IP is a comprehensive solution for verifying the standalone Adaptive Voltage Scaling Bus 2.0 protocol, a significant evolution of the AVSBus standard introducing multi-target support, extended frame formats, and enhanced power management capabilities for next-generation ASIC, FPGA, and processor power control designs. Fully compliant with the AVSBus version 2.0 specification, it supports complete verification of AVSBus 2.0 Controller and Target components across 3-wire interface configurations, covering all AVSBus 2.0 commands, single controller and multiple target topologies supporting up to 15 targets via 4-bit target addressing, broadcast addressing, and multiple link configurations with 48-bit long frames and data widths up to 96 bits.
SmartDV’s AVSBus 2.0 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With Abort frame functionality, clock pausing between command frames, Target status response frames, back-to-back command support, user response frames, comprehensive error injection across all AVSBus 2.0 error types, built-in functional coverage, and a complete test suite, SmartDV’s AVSBus 2.0 VIP enables verification teams to thoroughly validate next-generation multi-target adaptive voltage scaling designs for advanced ASIC, FPGA, processor, and SoC power management applications.
