SmartDV’s AVSBus Verification IP is a comprehensive solution for verifying the Adaptive Voltage Scaling Bus protocol, a high-speed dedicated interface enabling ASICs, FPGAs, and processors to rapidly control their supply voltages for dynamic voltage and frequency scaling. Fully compliant with the AVSBus specification as defined in PMBus version 1.3.1 Part III, it supports complete verification of AVSBus Master and Slave components across 3-wire and 2-wire interface configurations, covering all AVSBus commands, single master and single slave topologies, and multiple link configurations with data widths up to 64 bits.
SmartDV’s AVSBus VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With clock resynchronization, clock suspension, master alert generation, back-to-back command support, user response frames, comprehensive error injection across all AVSBus error types, built-in functional coverage, and a complete test suite, SmartDV’s AVSBus VIP enables verification teams to thoroughly validate adaptive voltage scaling designs for ASIC, FPGA, processor, and SoC power management applications.
