SmartDV’s AMBA AXI-Stream Synthesizable Transactor is a fully featured AMBA AXI-Stream bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable streaming source and sink behavior during pre-silicon validation and software bring-up. Fully compliant with the ARM AMBA AXI-Stream Protocol Specification, it delivers complete unidirectional streaming functionality across single byte, packet, and frame transfers, giving validation teams a drop-in synthesizable transactor ready for rapid integration into emulation and prototyping flows for DSP, video, packet processing, and machine learning datapath designs.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports all standard data stream forms including byte stream, continuous aligned stream, continuous unaligned stream, and sparse stream, along with transfer interleaving and stream upsizing, downsizing, and merging, enabling validation teams to exercise corner-case streaming behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its rich set of configuration parameters controlling AXI-Stream functionality, combined with on-the-fly protocol checking and testbench event notification, enable rapid deployment for early software bring-up and system-level validation regardless of the underlying emulation platform.
