AI & HPC
The race to build faster AI systems starts at the silicon level. Inference engines, training accelerators, and high-performance computing platforms are pushing the boundaries of what chips can do.
LPDDR6 Controller IP
Design IP
Next-Gen Memory IP - Early Access
LPDDR6 & DDR6 Controller IP and Verification IP
Controller IP and Verification IP for the next generation of memory interfaces. LPDDR6 ready now, DDR6 tracking the JEDEC draft specification, built for AI, mobile, and server SoC design teams who cannot afford to wait.
LPDDR6 Finalized JEDEC specification
DDR6 Aligned with JEDEC draft spec
2x Memory bandwidth vs previous gen
The Memory Bandwidth Challenge
AI workloads, next-generation mobile platforms, and high-performance server designs are all pushing memory bandwidth to its limits. LPDDR6 and DDR6 are the answer, delivering a generational leap in throughput and efficiency. LPDDR6 is already specified and DRAM vendors are actively sampling. DDR6 is close behind, with the JEDEC specification in its final stages. For SoC teams, the window to get ahead of verification is now. SmartDV has Controller IP and Verification IP for both, so your team starts on your timeline not the market’s.
Products
SmartDV’s LPDDR6 Controller IP is a specification-compliant, high-performance memory controller solution purpose-built for mobile, automotive, and AI-driven SoCs requiring next-generation bandwidth and power efficiency for LPDDR6 memory devices. Fully compliant with JEDEC...
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DDR6 Controller IP
Design IP
SmartDV’s DDR6 Controller IP provides early access to next-generation, high-bandwidth memory control for AI, HPC, and data-center SoCs, architected in alignment with the JEDEC JC-42 Committee’s current DDR6 working draft. As DDR6...
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LPDDR6 with DFI VIP
Simulation
SmartDV’s LPDDR6 Verification IP is a comprehensive solution for verifying the next-generation Low Power Double Data Rate 6 memory interface, the first JEDEC LPDDR standard to adopt a four 24-bit sub-channel architecture...
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DDR6 VIP
Simulation
SmartDV’s DDR6 Verification IP is a comprehensive early-access solution for verifying next-generation DDR6 SDRAM memory interfaces, enabling design and verification teams to begin DDR6 validation ahead of JEDEC final ratification. Developed in...
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Key Features
- LPDDR6 Controller IP compliant with the finalized JEDEC specification, designed for the high bandwidth and power efficiency demands of next-generation mobile and edge AI SoCs.
- DDR6 Controller IP developed in alignment with the JEDEC draft specification, targeting server, HPC, and AI accelerator designs where memory throughput is the critical performance factor.
- Verification IP for both LPDDR6 and DDR6, UVM-ready with comprehensive protocol coverage to enable design teams to begin memory subsystem verification ahead of silicon availability.
- Configurable and customizable through SmartDV's SmartCompiler engine, allowing the IP to be tailored to specific process nodes, performance targets, and integration requirements.
Applications
Consumer & Mobile
Every new smartphone, wearable, or gaming device raises the bar for what silicon can deliver. Consumer and mobile SoC teams are under constant pressure to pack more performance into less power and area.
IP Your Way
Customized with SmartCompiler
Unlike off-the-shelf IP from other vendors, SmartDV’s proprietary SmartCompiler engine lets our engineering team optimize every IP core to your exact design requirements.
Learn about custom IPTrusted by the Industry
400+ Customers worldwide
500+ Protocol IP products across the full design flow
350+ Experienced engineers behind every IP
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Talk with SmartDV about LPDDR6 & DDR6
Have a question about our LPDDR6 or DDR6 Controller IP or Verification IP? Drop us a note and the right person on our team will be in touch.