LPDDR6 with DFI VIP

Simulation

Benefits Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s LPDDR6 Verification IP is a comprehensive solution for verifying the next-generation Low Power Double Data Rate 6 memory interface, the first JEDEC LPDDR standard to adopt a four 24-bit sub-channel architecture delivering up to 50% higher bandwidth than LPDDR5X for mobile, AI edge, and automotive applications. Fully compliant with JEDEC JESD209-6 (published July 2025) and DFI 6.0 (published May 2026), it supports complete verification of LPDDR6 device components across x12 and x24 device modes with densities from 4 Gb to 64 Gb, covering all defined commands, sub-channel mode operation, multi-die package configurations, interleaved and gapless 64-byte access modes, WCK2CK sync, CA and CS training patterns, post package repair, refresh management, CA command parity, write and read metadata, and the DDR PHY Interface for LPDDR6 and next-generation memory protocols.

SmartDV’s LPDDR6 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive Dynamic Voltage Frequency Scaling for Low power, Dynamic Efficiency mode, dual bank and all-bank refresh, partial array self-refresh segment masking, write clock free running mode, frequency set point operation, fault diagnostics and notification, on-die ECC, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s LPDDR6 VIP enables verification teams to thoroughly validate LPDDR6 memory subsystem designs for flagship smartphones, 5G platforms, automotive ADAS, AR/VR, AI edge inference, and next-generation power-efficient computing applications.

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LPDDR6 with DFI VIP

Benefits

Complete LPDDR6 Device Protocol Coverage – Supports 100% of the LPDDR6 protocol standard per JEDEC JESD209-6, all LPDDR6 commands, x12 and x24 device modes, densities from 4 Gb to 64 Gb, WCK:CK ratio 2:1 for all frequencies, all defined data rates from 10,667 MT/s to 14,400 MT/s, burst lengths of 24 and 48, programmable read/write latencies, BG bank group mode, burst chunk and burst sequence, and programmable clock frequency of operation.
Sub-Channel and Multi-Die Architecture Support – Supports sub-channel mode operation with two 12-bit sub-channels per die forming the x24 device interface, multi-die package configurations, interleaved 64-byte access with 24-beat gap for speeds above 6400 Mbps, gapless 64-byte access for speeds at or below 6400 Mbps, on-the-fly burst length control between 32B and 64B access, and all mode register programming.
Metadata, Data Integrity, and RAS – Supports write and read metadata carried within the data packet for data mask, data bus inversion, and Link ECC without dedicated pins, write DBI and read DBI operation, WCK2CK sync operation, CA command with parity, on-die ECC, fault diagnostics and notification via four fault registers and a dedicated alert signal, per-row activation count for row-hammer mitigation, and programmable link protection scheme.
Training and Calibration Support – Covers CA and CS training patterns, WCK2CK sync training, dynamic write non-target ODT for signal integrity optimization, and all defined LPDDR6 interface training modes for complete PHY-level interface verification.
Comprehensive Refresh and Power Management – Supports optimized refresh, Refresh Management Command, Adaptive and Directed Refresh Management, dual bank and all-bank refresh, partial array self-refresh segment masking, power down mode, self-refresh operation, write clock free running mode, frequency set point operation, post package repair, Dynamic Voltage Frequency Scaling for Low power reducing VDD2 during low-frequency operation, Dynamic Efficiency mode for single sub-channel low-power operation, and input clock stop and frequency change.
DFI 6.0 PHY Interface Support – Compliant with DFI 6.0 (published May 2026) with native LPDDR6 protocol support including the new x24 sub-channel interface, high-performance PHY-to-controller interface enhancements for next-generation AI and mobile workloads, and expanded coverage for LPDDR6-specific features such as metadata transfer, fault notification, and sub-channel operation as defined in the DFI 6.0 specification.
Comprehensive Protocol Checking – Provides continuous bus-accurate monitoring of LPDDR6 device behavior during simulation for minimum, maximum, and typical timing values, covering power-on, initialization, power-off rules, state-based rules, active command rules, read and write command rules, and all timing violations, with protocol checker fully compliant with JESD209-6.
Complete Verification Infrastructure – Provides built-in functional coverage analysis, constraints randomization, all mode register programming support, and callbacks for user access to command data and monitor-observed data across all LPDDR6 and DFI 6.0 protocol conditions.

Compliance and Compatibility

Fully compliant with JEDEC JESD209-6 (LPDDR6, published July 2025)
Compliant with DFI 6.0 (published May 2026) with native LPDDR6 protocol support
Supports x12 and x24 device modes with densities from 4 Gb to 64 Gb
Supports data rates from 10,667 MT/s to 14,400 MT/s
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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