SmartDV’s DDR6 Verification IP is a comprehensive early-access solution for verifying next-generation DDR6 SDRAM memory interfaces, enabling design and verification teams to begin DDR6 validation ahead of JEDEC final ratification. Developed in alignment with the JEDEC DDR6 draft specification targeting data rates from 8,800 MT/s to 17,600 MT/s and featuring a quad 24-bit sub-channel architecture, it supports complete verification of DDR6 device components across x4, x8, and x16 device widths with densities up to 64 GB and 64 banks on die, covering all DDR6 commands, refresh management, Post Package Repair, and all timing delay ranges as defined in the current draft specification.
SmartDV’s DDR6 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive refresh management verification including ARFM, DRFM, and PASR, advanced Post Package Repair coverage including hard, soft, and MBIST PPR, MRUPD mode support, bus-accurate timing for all timing delay ranges, built-in functional coverage, and a complete test suite, SmartDV’s DDR6 VIP enables verification teams to begin thorough DDR6 memory interface validation for next-generation AI, data center, server, and high-performance computing applications ahead of final spec ratification.
