SmartDV’s SLVS-EC Verification IP is a comprehensive solution for verifying Scalable Low Voltage Signaling with Embedded Clock, the Sony Semiconductor Solutions developed and JIIA standardized high-speed serial interface connecting CMOS Image Sensors to Digital Signal Processors in industrial, machine vision, and high-resolution imaging applications. Fully compliant with SLVS-EC Specification Version 3.1 and backward compatible with Versions 3.0, 2.0, and 1.2, it supports complete verification of SLVS-EC Transmitter and Receiver devices across Basic, Multiple I/F, and Multiple CIS system topologies, all four defined frame synchronization schemes, multi-lane configurations from 1 to 8 lanes, RAW 8, 10, 12, 14, and 16-bit color formats, embedded data transfer, and multiple stream transfer.
SmartDV’s SLVS-EC VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With LINK and PHY protocol management, 8B/10B encoding and decoding, Gigabit Channel Coding (GCC) for reduced overhead transmission, Forward Error Correction, Error Correction Code, Cyclic Redundancy Check, skew and jitter insertion, comprehensive error injection and detection, built-in functional coverage, and a complete test suite, SmartDV’s SLVS-EC VIP enables verification teams to thoroughly validate SLVS-EC interface designs for industrial cameras, machine vision systems, automotive imaging, and high-resolution, high-frame-rate CMOS image sensor applications.
