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Overview

SmartDV’s Safe-By-Wire Plus Verification IP is a comprehensive solution for verifying the Safe-By-Wire Plus two-wire serial communications bus, the automotive industry standard for connecting airbag crash sensors, occupant sensors, and satellite modules to airbag electronic control units via a power-superposing daisy chain bus that reduces vehicle harness count while delivering fault-tolerant, deterministic safety communication. Adherent to Safe-By-Wire Plus Specification Version 2.0 (September 2004), it supports complete verification of SBWP Master and Slave components across the twisted-pair differential daisy chain bus topology, time slot communication system guaranteeing deterministic message delivery, power supply and communication phase operation, bidirectional master-to-slave and slave-to-master communication, all defined frame types, deployment message generation, error and noise injection, and bit error detection by both master and slave.

SmartDV’s SBWP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With transmit and receive counter tracking, comprehensive protocol checking fully compliant with SBWP v2.0, bus-accurate timing, constraints randomization, built-in functional coverage, and a complete test suite, SmartDV’s Safe-By-Wire Plus VIP enables verification teams to thoroughly validate SBWP sensor bus interface designs for automotive airbag ECUs, belt pretensioner control units, occupant protection systems, and ISO 26262-compliant passive safety control applications.

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Key Features
  • Full SBWP Master and Slave Support – Provides complete Safe-By-Wire Plus Master and Slave component verification across the two-wire twisted-pair differential daisy chain bus topology, supporting power superposing operation where both power supply and communication share the same two wires, bidirectional master-to-slave downlink and slave-to-master uplink communication, and transmit and receive counter tracking.
  • Time Slot Communication SystemSupports time slot based communication ensuring guaranteed deterministic delivery of all defined frame types within fixed time bounds, covering power supply phase and communication phase operation, deployment message generation including high-speed deployment messages initiated by the master, and all defined master-to-slave configuration and control sequences.
  • Daisy Chain Topology and Fault Tolerance – Supports daisy chain connected slave configurations where sensor satellites are coupled in series, fault tolerance through slave bypass and isolation mechanisms enabling upstream slaves to continue operating when a downstream slave develops a fault, and all defined slave addressing and enumeration sequences.
  • Frame Generation with Error and Noise Injection – Supports generation of all defined SBWP frame structures with configurable payload, error and noise injection at the frame level across all defined error types and noise conditions, and bit error detection by both master and slave across all defined frame positions for complete SBWP robustness and fault tolerance verification.
  • Comprehensive Protocol CheckingProvides continuous bus-accurate monitoring of SBWP bus behavior during simulation with a protocol checker fully compliant with Safe-By-Wire Plus v2.0, covering all defined protocol timing requirements, time slot rules, sequence rules, and error conditions, detecting and notifying the testbench of all protocol violations.
  • Complete Verification Infrastructure – Provides a full test suite covering all Safe-By-Wire Plus v2.0 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in master, slave, and monitor for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Adherent to Safe-By-Wire Plus Specification Version 2.0 (September 2004)
  • Supports two-wire power-superposing daisy chain topology with time slot communication
  • Supports master and slave bit error detection across all defined frame types
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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