SmartDV’s RapidIO Verification IP is a comprehensive solution for verifying the RapidIO high-performance packet-switched interconnect, the open standard for chip-to-chip, board-to-board, and system-to-system communication in embedded, wireless infrastructure, defense, and high-performance computing applications. Fully compliant with RapidIO Specifications 4.1 and backward compatible through Revisions 4.0, 3.2, 3.1, 3.0, 2.2, 2.1, 2.0, and 1.3, it supports complete verification of RapidIO Host and Device components across serial 1x, 2x, 4x, 8x, and 16x lane configurations at all defined baud rates from 1.25 Gbaud through 25.78125 Gbaud, parallel 8/16-bit interfaces, 8b/10b and 64b/67b encoding, all device ID widths, all transaction types across I/O system, message passing, and globally shared distributed memory models, and Error Management Extensions.
SmartDV’s RapidIO VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive flow control, out-of-order transaction delivery, critical request flow ordering, packet cancellation and retry, scrambler/descrambler support, flexible serial lane error injection, comprehensive error detection and status counters, built-in functional coverage, and a complete test suite, SmartDV’s RapidIO VIP enables verification teams to thoroughly validate RapidIO interconnect designs for wireless baseband processing, 4G/5G infrastructure, military computing, high-performance embedded systems, and space avionics applications.
