SmartDV’s RapidIO Synthesizable Transactor is a fully featured RapidIO packet-based interconnect bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable RapidIO Endpoint and Switch behavior during pre-silicon validation of wireless infrastructure, defense, high-performance computing, and embedded systems designs. Fully compliant with RapidIO v4.1 (VITA) and backward compatible with RapidIO v2.0 through v4.0, it delivers complete Endpoint and Switch functionality across 1x, 2x, and 4x physical lane configurations at lane rates from 1.25 Gbaud to 6.25 Gbaud with Gen4 support up to 25 Gbps per lane, giving validation teams a drop-in synthesizable RapidIO transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports I/O system operations, message passing via mailboxes, Globally Shared Memory access, all RapidIO packet types and sizes, all IDLE sequences, Control and Status Symbols, flow control generation and reaction, out-of-order transaction delivery based on prioritization, critical request flow ordering, 34, 50, and 66-bit addressing, 8-bit and 16-bit device IDs, and automatic resource freeing for acknowledged packets, enabling validation teams to exercise corner-case RapidIO behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform. Its comprehensive interrupt support, per-error-type interrupt generation, all Capability Registers and Configuration and Status Registers, and testbench notification of significant events, warnings, timing, and protocol violations enable rapid deployment for early software bring-up and RapidIO system-level validation regardless of the underlying emulation platform.
