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Overview

SmartDV’s MIPI SoundWire Verification IP is a comprehensive solution for verifying the MIPI SoundWire double data rate audio bus interface, a low-complexity, low-power, multi-drop serial interface supporting PCM and PDM audio data transport between a Manager and multiple Peripheral devices. Fully compliant with MIPI SoundWire v1.3 (September 2025) and backward compatible with v1.2r08 and earlier revisions, it supports complete verification of SoundWire Manager, Peripheral, and Monitor components across Basic PHY and High PHY modes, all defined frame shapes with static, dynamic, and PHY frame synchronization, all command types, all transport modes including multi-lane payload, flow-controlled payload, and bulk payload, and comprehensive error injection and detection across all defined SoundWire error types.

SmartDV’s MIPI SoundWire VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With dual ranked register and commit mechanism, multi-byte quantities buffer, dynamic shape and payload switching, group response handling, PRBS and static test modes, clock pause and stop, all reset types, built-in functional coverage, and a complete test suite, SmartDV’s MIPI SoundWire VIP enables verification teams to thoroughly validate SoundWire audio bus interface designs for smartphones, tablets, PCs, automotive infotainment, and embedded audio systems using amplifiers, microphones, and audio codecs.

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MIPI SoundWire VIP
Key Features
  • Full Manager, Peripheral, and Monitor Support – Provides complete SoundWire Manager, Peripheral, and Monitor component verification across Basic PHY and High PHY modes, supporting bus control handover to Monitor based on BREQ bit, BANK handling, all combinations of ACK/NACK responses, PING, Read, and Write commands, and bus clock speed encoding.
  • Comprehensive Frame and Synchronization Coverage – Supports all defined SoundWire frame shapes with static, dynamic, and PHY frame synchronization, dynamic shape and payload switching, IO timing, and all register definitions with proper read/write attributes including Dual Ranked Register and Commit mechanism and Multi-byte Quantities buffer.
  • Transport Mode Coverage – Supports multi-lane payload transport, all types of payload positioning with respect to Block per Port and Block per Channel, all types of flow-controlled payload transport, bulk payload transport, and bulk register access for complete SoundWire data plane verification.
  • Group, Interrupt, and Power Management Support – Supports group and group response generation and handling, all defined interrupt types, bus clock speed encoding, clock pause operation, and clock stop operation for complete SoundWire system management verification.
  • Test Mode and Reset Support – Supports PRBS, Static0, and Static1 test modes, and all defined reset types including Bus-Reset, ClockStopMode1 Reset, LostSync Reset, and Register Reset for complete SoundWire initialization and recovery verification.
  • Comprehensive Error Injection and Detection – Supports injection and detection of all defined SoundWire error types including Functional Parity errors, CRC errors, Dynamic Sync bit errors, Static Sync bit errors, Peripheral responding when address not assigned, Manager startup using wrong shape, bus clash error, PRBS pattern error, Testmode Static 0 error, and Testmode Static 1 error.
  • Complete Verification Infrastructure – Provides a full test suite covering all MIPI SoundWire v1.3 specification features, built-in functional coverage analysis, status counters for bus events, and callbacks in Manager, Peripheral, and Monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with MIPI SoundWire v1.3 (September 2025); backward compatible with v1.2r08 and earlier revisions
  • Supports Basic PHY and High PHY operating modes
  • Supports all defined frame shapes with static, dynamic, and PHY frame synchronization
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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