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Overview

SmartDV’s MIPI SoundWire I3S Peripheral IP is a high-performance audio interface solution purpose-built for audio peripheral SoC designs requiring unified, high-bandwidth audio streaming and control across mobile, automotive, consumer electronics, and industrial applications. Fully compliant with MIPI SWI3S v1.0, it delivers complete peripheral-side I3S functionality over a two-pin interface at data rates up to 76 Mbps, enabling next-generation audio peripherals such as smart microphones, amplifiers, and codec devices to replace legacy I2S, TDM, and HDA interfaces with a single, scalable, power-efficient solution.

Designed for the demanding requirements of modern embedded audio peripheral designs, the IP supports up to 32 data ports with 16 channels each, FBCSE and DLV PHY modes, NRZS and 8b/10b encodings, and a comprehensive error detection suite covering Bad8b10b, BadHD10, BadCRC, Missed Row Sync, Invalid Phase ID, and Invalid Packet Length errors. Its Dormant mode support, sleep/wake cycle management, and FBCSE clock pause operation make it particularly well-suited for power-sensitive mobile and wearable audio peripheral designs where standby power consumption is a critical constraint.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, multiple PHY options, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and audio peripheral applications.

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MIPI SoundWire I3S Peripheral
Benefits
  • Full MIPI SWI3S Peripheral Functionality – Complete peripheral-side implementation per MIPI SWI3S v1.0 supporting up to 76 Mbps over a two-pin interface with half-duplex operation
  • High-Capacity Data Port Support – Up to 32 data ports with 16 channels each for comprehensive multi-stream audio peripheral connectivity
  • Multiple PHY Support – FBCSE for PHY1 and PHY2 and DLV for PHY3 with both-edges sampling for FBCSE, providing flexible physical layer options for diverse deployment scenarios
  • Dual Encoding Support – NRZS and 8b/10b encoding for flexible, application-specific physical layer implementation
  • Comprehensive Error Detection – Bad8b10b, BadHD10, BadCRC, Missed Row Sync, Invalid Phase ID, and Invalid Packet Length error detection for robust peripheral operation
  • Comprehensive Flow Control – Normal, Source Controlled, Sink Controlled, and Sink-Source Controlled transport modes for complete audio stream management
  • Full Command Support – Ping, Read, Write, Commit, Announce, and CalibratePhy commands with Dual Ranked Register and Commit mechanism for reliable register management
  • Advanced Power Management – Dormant mode, sleep/wake cycle, cold boot, wake-up request, and FBCSE clock pause operation for power-optimized peripheral operation
  • Comprehensive Reset Support – Bus Reset, Cold Reset, Warm Reset, and Power-On Reset for robust system initialization and recovery
Compliance and Compatibility
  • Fully compliant with MIPI SoundWire I3S v1.1 r02 draft specification
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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