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Overview

SmartDV’s MIPI SoundWire I3S Verification IP is a comprehensive solution for verifying the SoundWire I3S interface, a scalable two-wire audio streaming and control interface designed for high-bandwidth, low-latency multichannel audio applications. Fully compliant with MIPI SWI3S v1.0, it enables accurate and efficient verification of synchronized audio transport between SoCs and external audio components across FBCSE and DLV PHY modes.

SmartDV’s MIPI SoundWire I3S VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With configurable Manager and Peripheral agents, frame-based transfer support, synchronized channel handling, integrated protocol checkers, and detailed coverage metrics, SmartDV’s MIPI SoundWire I3S VIP enables verification teams to thoroughly validate high-bandwidth multichannel audio interfaces for mobile, automotive, and professional audio applications.

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MIPI SoundWire I3S VIP
Benefits
  • Comprehensive Manager, Peripheral, and Monitor Functionality – Provides full SWI3S Manager BFM that initiates frame transactions based on user-driven commands, Peripheral agents that synchronize to the bus and process programmed slots, and an integrated Monitor that observes all bus activities and tracks access statistics.
  • Accurate PHY and Protocol Modeling – Supports PHY 1 (FBCSE 0), PHY 2 (FBCSE 1), and PHY 3 (DLV) modes with NRZS and 8b/10b encoding, FBCSE clock-pause operation, and I/O timing checks for precise physical layer verification.
  • Scalable Multi-Peripheral Topology Support – Supports up to 12 Peripherals, each with 32 data ports and 16 channels per port, enabling large-scale verification of complex multi-node audio topologies.
  • Robust Error and Interrupt Verification – Generates and detects Manager and Peripheral errors including CRC, Invalid Packet Length, Opcode, PHY Number, Phase ID, and Row Delay errors, with interrupt handling and event counters for each error scenario.
  • Advanced Monitoring and Coverage – Detects protocol and timing violations, implements a comprehensive functional coverage model, and notifies the testbench of significant events including transactions, warnings, and protocol violations.
  • Customizable Testbench Control – Offers a rich set of APIs and callbacks for user-defined packet generation, event monitoring, and data processing, with error injection support via callbacks for flexible verification scenario development.
  • Complete Verification Infrastructure – Provides a full regression test suite covering all SoundWire I3S specification features, functional coverage analysis, and constraints randomization for thorough verification of all protocol conditions.
Compliance and Compatibility
  • Fully compliant with MIPI SoundWire I3S v1.0 (MIPI SWI3S v1.0, September 2025)
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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