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Overview

SmartDV’s MIPI SoundWire I3S Synthesizable Transactor is a fully featured MIPI SWI3S audio interface bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable SoundWire I3S Manager and Peripheral behavior during pre-silicon validation of mobile, consumer, automotive, and industrial audio subsystem designs. Fully compliant with MIPI SWI3S v1.0, it delivers complete Manager and Peripheral functionality supporting data rates up to 76 Mbps over a unified two-pin interface, giving validation teams a drop-in synthesizable SWI3S transactor ready for rapid integration into emulation and prototyping flows for next-generation embedded audio system validation.

Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports both LVDS PHY for higher speed operation and single-ended CMOS PHY for lower speed systems, 8b/10b encoding and decoding, all transfer types including Info, Read, Write, Multicast Write, Multicast Commit, and Multi-Phase Read, row-based bitstream structure, PDM and PCM data encodings, in-band interrupt and wake-up signaling, system-wide stream synchronization, and embedded command channel operation, enabling validation teams to exercise corner-case SWI3S behavior that is difficult to reach with production RTL alone.

Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its comprehensive transport and protocol error detection including bad symbol, bad token, bad HD10 token, CRC, unexpected token, and unexpected phase errors, combined with status counters for all bus events and testbench notification of protocol and timing errors, enable rapid deployment for early software bring-up and audio system-level validation regardless of the underlying emulation platform.

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MIPI SoundWire Transactor
Benefits
  • Full MIPI SWI3S Manager and Peripheral Model – Complete Manager and Peripheral behavior per MIPI SWI3S v1.0 supporting one Manager and up to 12 Peripherals per link over a unified two-pin interface
  • Dual PHY Support – LVDS PHY for higher speed operation up to 76 Mbps and single-ended CMOS PHY for lower speed systems, covering the full SWI3S deployment range
  • Comprehensive Transfer Type Coverage – Info, Read, Write, Multicast Write, Multicast Commit, and Multi-Phase Read transfers for complete SWI3S protocol validation coverage
  • Audio Data Support – Multiple channel support with both PDM and PCM data encodings and row-based bitstream structure for complete audio payload transport validation
  • 8b/10b Encoding and Decoding – Complete 8b/10b encoding and decoding per SWI3S specification for physical layer validation
  • In-Band Signaling – In-band interrupt condition signaling and in-band wake-up request signaling for complete bus event validation
  • System Synchronization – System-wide stream synchronization support for precise multi-device audio timing validation
  • Embedded Command Channel – Embedded command channel for reading and writing control parameters and reporting status for complete control plane validation
  • Transport and Protocol Error Detection – Bad symbol, bad token, bad HD10 token, CRC, unexpected token protocol, and unexpected phase protocol error detection with status counters and testbench notification of all protocol and timing errors
  • Reset and Link Power Management – Full reset and link power management modeling for complete SWI3S power state validation
Compliance and Compatibility
  • Fully compliant with MIPI SWI3S v1.0 specification (October 2025); developed from draft v0.4r06
  • Uses current MIPI Alliance terminology: Manager (formerly Master) and Peripheral (formerly Slave)
  • Fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform
  • Vendor-agnostic integration suitable for Synopsys, Cadence, Siemens, and custom emulation and prototyping environments
  • Configurable interface supporting integration into custom emulation and prototyping testbenches

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