SmartDV’s I2C Synthesizable Transactor is a fully featured Inter-Integrated Circuit bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable I2C Master and Slave behavior during pre-silicon validation and software bring-up. Fully compliant with I2C v7.0, it delivers complete Master and Slave functionality with the flexibility to operate as Master only, Slave only, or both simultaneously, across Standard, Fast, Fast-mode Plus, and High-speed operation, giving validation teams a drop-in synthesizable I2C transactor ready for rapid integration into emulation and prototyping flows for sensor, EEPROM, and peripheral system validation.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports 7-bit and 10-bit configurable slave addressing, complex repeated start command sequences, multi-master bus arbitration, multiple slave support, wait state insertion by both master and slave, START byte generation and handling, and bus-accurate timing, enabling validation teams to exercise corner-case I2C behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its built-in AT24C1024 EEPROM memory model, comprehensive error injection capabilities, and complete testsuite covering every feature of the I2C specification enable rapid deployment for early software bring-up and system-level validation regardless of the underlying emulation platform.
