Contact Us
Overview

SmartDV’s HDMI eARC Receiver IP is a fully featured Enhanced Audio Return Channel receiver solution purpose-built for SoC designs requiring reliable, high-fidelity audio return connectivity across TV, AV receiver, and soundbar applications. Compliant with the HDMI eARC protocol standard as defined in HDMI Specification 2.2, it delivers complete eARC receiver functionality with single-ended non-differential split outputs, supporting the reception of both encrypted and unencrypted 2-channel and multi-channel L-PCM, IEC 61937, and one-bit audio formats.

Designed for the practical integration requirements of modern AV receiver and soundbar SoC designs, the IP supports ACP, ISRC1, and ISRC2 U-bit message structures, ECC (Error Correcting Code) decoding and error correction, biphase-mark decoding, and falling-edge de-modulation. Its complete eARC Common Mode Data Channel function support including discovery and disconnect, heartbeat, status bits, audio latency control, and capabilities data structure give AV SoC teams a production-ready eARC receiver implementation for the latest high-bitrate, uncompressed multi-channel audio formats including Dolby Atmos and DTS:X.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.

Request Data Sheet
HDMI eARC Receiver
Key Features
  • Full HDMI eARC Receiver Functionality – Complete eARC receiver implementation per HDMI Specification 2.2 with single-ended non-differential split outputs
  • Comprehensive Audio Format Support – Reception of encrypted and unencrypted 2-channel L-PCM, multi-channel L-PCM, IEC 61937, and one-bit audio formats
  • U-Bit Message Structure Support – ACP, ISRC1, and ISRC2 U-bit message structure reception for complete metadata handling
  • Error Correcting Code – Complete ECC decoding and error correction for reliable audio data integrity
  • Biphase-Mark Decoding – Complete biphase-mark decoding with falling-edge de-modulation for accurate signal reception
  • Common Mode Data Channel Support – Complete discovery and disconnect, heartbeat, status bits, audio latency control, and capabilities data structure functionality over the eARC CMDC
Compliance and Compatibility
  • Compliant with HDMI eARC protocol standard as defined in HDMI Specification 2.2
  • Backward compatible with eARC as defined in HDMI Specification 2.1
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

Request Datasheet