Contact Us
Overview

SmartDV’s HDMI Verification IP is a comprehensive solution for verifying the High-Definition Multimedia Interface across the complete HDMI specification family, from HDMI 1.4b through the latest HDMI 2.2. Fully compliant with HDMI Specification 2.2 and backward compatible with HDMI 2.1b, 2.1a, 2.1, 2.0b, and 1.4b, it supports complete verification of HDMI source and sink device functionality across TMDS at 340 Mcsc to 600 Mcsc character rates and Fixed Rate Link transmission at 3, 6, 8, 10, and 12 Gbps per lane, covering all video, data island, and control period modes, all packet formats, eARC, VRR, FVA, Display Stream Compression, 3D, 4K through 10K resolutions, CEC 2.0, DDC, HEAC, and comprehensive HDCP 1.4, 2.2, and 2.3 content protection.

SmartDV’s HDMI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive FRL feature coverage including character error detection, FEC, 16b18b coding, Source-Based Tone Mapping, IDCC protocol, SCDS and EEODB support, PCA, OVT-based timings, CTA-861-I compliance, DVI 1.0 compatibility, extensive error detection, built-in functional coverage, and a complete test suite, SmartDV’s HDMI VIP enables verification teams to thoroughly validate HDMI interface designs for consumer electronics, gaming displays, home theater, automotive infotainment, and professional AV applications.

Request Data Sheet
HDMI VIP
Benefits
  • Full HDMI Source and Sink Device Support – Provides complete HDMI source and sink device functionality across serial and symbol interfaces, supporting TMDS character rates from 340 Mcsc to 600 Mcsc, FRL lane link rates of 3, 6, 8, 10, and 12 Gbps, all three operating modes including video period, data island period, and control period, TERC4 coding, control period coding, serialization and deserialization, and display data channel support.
  • HDMI 2.2 and FRL Feature SupportSupports Fixed Rate Link transmission with FRL character error detection, FRL content protection, Forward Error Correction, and 16b18b coding, enabling complete verification of HDMI 2.2 96 Gbps bandwidth operation with next-generation FRL technology supporting resolutions up to 12K@120 and 16K@60.
  • Resolution and Video Format Coverage – Supports 3D, 4Kx2K, 5Kx2K, 8Kx4K, and 10Kx4K resolutions, expanded color spaces, Variable Refresh Rate, Fast VActive, Compressed Video Transport per VESA DSC 1.2a, Source-Based Tone Mapping, OVT-based timings from CTA-861-I, and Video Timing Data Block support.
  • Audio and ARC SupportSupports Audio Return Channel, Enhanced Audio Return Channel, new audio CODECs, CTA-861-F/CTA-861-G/CTA-861-H/CTA-861-I audio standards, and HDMI Ethernet and Audio Return Channel, providing comprehensive audio path verification across all HDMI generations.
  • HDMI 2.1 Advanced Feature SupportCovers Consumer Electronics Control 2.0, ID Communications Channel protocol over DDC for source and cable communication, Sink Capabilities Data Structure and EDID Extensible Override Data Block, Power for Cable Assemblies, HDMI Type B Connector Dual-Link Architecture, and all packet formats as per HDMI 2.1, 2.1a, and 2.1b specifications.
  • Content Protection and Standards Compliance – Supports HDCP 1.4, 2.2 with full authentication and bypass, and 2.3, CTA-861-F through CTA-861-I standards, data island ECC, and DVI 1.0 single-link and dual-link architecture compatibility.
  • Comprehensive Error Detection and Reporting – Detects and reports invalid control characters, invalid data characters, invalid 10-bit codes, sync errors, ECC errors, and invalid packing injection and detection across all HDMI protocol layers and operating modes.
  • Complete Verification Infrastructure – Provides a full test suite covering all HDMI specification features through HDMI 2.2, built-in functional coverage analysis, status counters for bus events, and callbacks in transmitter and receiver for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with HDMI Specification 2.2; backward compatible with HDMI 2.1b, 2.1a, 2.1, 2.0b, and 1.4b
  • Supports TMDS at 340 Mcsc to 600 Mcsc and FRL at 3, 6, 8, 10, and 12 Gbps per lane
  • Supports HDCP 1.4, 2.2, and 2.3 content protection
  • Supports CTA-861-F through CTA-861-I standards
  • Compatible with DVI 1.0 single-link and dual-link architecture
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

Request Datasheet