SmartDV’s HBM2 Controller IP is a fully featured High Bandwidth Memory controller solution purpose-built for SoC designs requiring extreme memory bandwidth across AI/ML accelerator, GPU, and high-performance computing applications. Supporting HBM2 per JESD235 and JESD235A and HBM2E per JESD235B, JESD235C, and JESD235D (revisions 2.60 through 4.20), and compliant with DFI v4.0 or v5.0, it delivers complete controller functionality supporting up to 16 AXI ports with data widths up to 512 bits, channel densities from 1GB to 128GB, and up to 8 channels per stack.
Designed to maximize memory bandwidth in demanding AI and HPC SoC designs, the IP supports configurable open and closed page policies, transaction reordering, in-port and multi-port arbitration, burst lengths of 2 and 4, all interface groups, programmable Read/Write latency timings, bank grouping, legacy mode and pseudo channel mode operation, and self-refresh modes. Its Extended Addressing, Extended Write and Read latency, Data Bus Inversion, Command/Address and Data parity (HBM2E), write data mask and data strobe features, and IEEE 1500 support give AI and HPC SoC teams a production-tested, spec-complete HBM2/HBM2E controller for the most demanding memory bandwidth requirements.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized AXI port count and bus-accurate timing model for min, max, and typical values enable fast integration across a wide range of AI and HPC process nodes.
