SmartDV’s HBM2E Verification IP is a comprehensive solution for verifying High Bandwidth Memory 2E interfaces, delivering the high bandwidth and low power consumption required by GPU, AI accelerator, HPC, and networking SoC designs. Fully compliant with JEDEC JESD235D and backward compatible with JESD235C, JESD235B, and JESD235 (HBM1), it supports complete verification of HBM2E device components across up to 8 channels per stack with channel densities from 1 GB to 128 GB, covering legacy mode and pseudo-channel mode operation, 128 DQ width with optional ECC per channel, DBIac, extended addressing, extended read and write latency, command and address parity, data parity, and IEEE 1500 standard test access.
SmartDV’s HBM2E VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive bank group support, write data mask and data strobe features, self-refresh modes, target row refresh, temperature compensated refresh reporting, bus-accurate timing for all delay ranges, built-in functional coverage, and a complete test suite, SmartDV’s HBM2E VIP enables verification teams to thoroughly validate high-bandwidth 3D stacked memory interface designs for discrete GPUs, AI training accelerators, high-performance computing, and bandwidth-intensive networking applications.
