SmartDV’s HBM3 Controller IP is a fully featured High Bandwidth Memory controller solution purpose-built for SoC designs requiring the highest available memory bandwidth across AI/ML accelerator, GPU, and high-performance computing applications. Supporting JEDEC HBM3 per JESD238 and JESD238A and compliant with DFI v4.0 or v5.0, it delivers complete controller functionality supporting up to 16 AXI ports with data widths up to 512 bits, data rates up to 6.4 Gb/s per pin, and up to 16 channels per stack with two pseudo channels each for virtually 32 channels of independent access.
Designed to maximize memory bandwidth in the most demanding AI and HPC SoC designs, the IP supports configurable open and closed page policies, transaction reordering, in-port and multi-port arbitration, burst length of 8, bank grouping across up to 64 banks per pseudo channel, semi-independent row and column command interfaces, and 1:4, 1:2, and 1:1 Controller to DFI PHY frequency ratios. Its Command/Address and Data parity, WDQS-to-CK training, Data Bus Inversion (DBIac), Pseudo Channel Mode operation, and IEEE 1500 support give AI and HPC SoC teams a production-tested, spec-complete HBM3 controller for the highest-bandwidth memory subsystem designs in the industry.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized AXI port count and bus-accurate timing model for min, max, and typical values enable fast integration across a wide range of AI and HPC process nodes.
