SmartDV’s HBM3 Verification IP is a comprehensive solution for verifying High Bandwidth Memory 3 interfaces, delivering up to 819 GB/s per device for the most demanding GPU, AI accelerator, and HPC memory bandwidth requirements. Fully compliant with JEDEC JESD238B.01 and backward compatible with JESD238A and JESD238, it supports complete verification of HBM3 device components across up to 16 channels per stack with 2 pseudo-channels per channel, channel densities from 2 GB to 32 GB, covering pseudo-channel mode operation with 32 DQ width, semi-independent row and column command interfaces, 2KB page size per channel, command and address parity, data parity, DBIac, WDQS-to-CK training, and IEEE 1500 standard test access.
SmartDV’s HBM3 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive bank group support, symbol-based on-die ECC with real-time reporting, write data mask and data strobe features, self-refresh modes, bus-accurate timing for all delay ranges, built-in functional coverage, and a complete test suite, SmartDV’s HBM3 VIP enables verification teams to thoroughly validate HBM3 and HBM3E memory interface designs for AI training and inference accelerators, data center GPUs, high-performance computing clusters, and bandwidth-intensive server applications.
