SmartDV’s Ethernet 800G PCS IP is a fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring the highest ratified Ethernet bandwidth across AI training cluster, hyperscale data center, and GPU interconnect applications. Fully compliant with IEEE 802.3df-2024, the formal ratified 800 Gigabit Ethernet standard, it delivers complete 800GBASE-R PCS functionality across 32 PCS lanes (organized as dual 16-lane PCS instances), with 64b/66b encoding and decoding for backplane, copper, and optical configurations including 800GBASE-KR8, 800GBASE-CR8, 800GBASE-DR8, and 800GBASE-SR8.
Designed to address the extreme bandwidth and signal integrity demands of modern AI and hyperscale data center interconnects, the IP implements complete block synchronization and alignment marker lock, alignment marker insertion and removal, PCS lane deskew and reordering, gearbox functionality for various data widths, RS-FEC interleaving across the dual PCS instance architecture, and dedicated bit error rate monitoring and link fault detection. Its architecture aligned with IEEE 802.3df-2024’s refined link training seeding and PCS-to-PMA lane mapping for improved noise immunity, alongside support for IEEE 802.3az Energy Efficient Ethernet, give hyperscale AI infrastructure SoC teams a spec-complete 800G PCS implementation built to the ratified industry standard.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized PMA interface architecture and clean host interface enable fast integration across a wide range of hyperscale data center process nodes.
