SmartDV’s AVSBus 1.x Slave IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus slave solution purpose-built for Point of Load voltage regulator SoC designs requiring reliable, low-latency response to AVSBus master voltage commands. Fully compliant with AVSBus v1.3 (PMBus Part III), it delivers complete slave-side AVSBus functionality over a two-wire or three-wire SPI-like interface at bus speeds up to 50 MHz, enabling fast, deterministic voltage command reception and status response generation for power-optimized POL voltage regulator designs.
Designed for the demanding requirements of modern POL voltage regulator SoC designs, the IP supports all AVSBus commands and data types, clock resynchronization, clock suspension, asynchronous slave alert generation via AVS_SData pull-low, back-to-back command handling, user response frames, status response generation, timeout detection, and frame alignment. Its simple three-wire interface with AVS_MData, AVS_SData, and AVS_Clock signals minimizes integration complexity while delivering the sub-microsecond command response latency needed for effective adaptive voltage scaling in high-performance power management designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its broad SoC bus interface support and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
