AVSBus Master IP

Design IP

Overview

SmartDV’s AVSBus Master IP is a silicon-proven solution designed to enable efficient, high-speed communication between power management controllers and voltage regulators in advanced SoC designs. Fully compliant with the PMBus specification and AVSBus protocol, it plays a key role in dynamic voltage and frequency scaling (DVFS), helping to optimize power consumption and system performance in real time.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its compact footprint and robust feature set make it ideal for a wide range of power-sensitive applications, including mobile, automotive, and high-performance computing systems.

Benefits

Power-Efficient Voltage Management – Enables dynamic voltage control using AVSBus protocol for optimized performance and power consumption
2-Wire and 3-Wire Mode Support – Offers flexibility to match system design requirements and layout constraints
High Bus Efficiency – Supports multiple back-to-back frames and status responses to maximize bus utilization and responsiveness
Extensive Command Handling – Supports up to 256 AVSBus commands and responses for broad control and telemetry coverage
Flexible Clocking and Timing – Supports clock pausing between command frames and slave status response frames for enhanced timing control
Full Protocol Coverage – Implements all AVSBus-defined commands and data types as per the latest specification

Compliance and Compatibility

Fully compliant with PMBus™ AVSBus protocol, including versions 1.0, 1.4, and 2.0
Compatible with all major EDA synthesis, simulation, and linting flows

Related Products

AVSBus Slave IP

PMBus Master IP

PMBus Slave IP

AVSBus VIP

PMBus VIP

AVSBus Transactor

PMBus PSVIP