Blog
Explore technical insights, verification strategies, and industry perspectives from SmartDV. The SmartDV Blog covers Verification IP, Design IP, protocol standards, memory and interface technologies, verification methodologies, and emerging semiconductor trends to help engineering teams address increasingly complex SoC, ASIC, and FPGA development challenges.
Design IP & Customization
UCIe Bridge IP: Connecting AXI, CHI, CXL, PCIe, & CXS Across Chiplets
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Design IP & Customization
UCIe Controller IP vs. UCIe Bridge IP: What Does a Chiplet Design Need?
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Verification IP (VIP) & Solutions
CXL 4.0 Verification for AI and HPC Systems
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Verification IP (VIP) & Solutions
Ultra Ethernet Verification for AI and HPC Networks
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Verification IP (VIP) & Solutions
10BASE-T1S Verification for Automotive Ethernet
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Design IP & Customization, Verification IP (VIP) & Solutions
OpenGMSL Verification for Automotive SerDes Links
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Design IP & Customization, Verification IP (VIP) & Solutions
MIPI CSI-2 and DSI-2 Verification Guide
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Verification IP (VIP) & Solutions
Why UCIe Verification Is Critical for Chiplet-Based SoC Design
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Memory & DDR
HBM and LPDDR6 Verification Challenges for AI, HPC, and Edge Computing
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Design IP & Customization
Flexible IP Licensing and Customizable IP: What SoC Teams Should Consider
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Verification IP (VIP) & Solutions
How Reusable Verification IP Supports Scalable SoC Verification
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Memory & DDR
How Memory Models Improve DDR and SoC Verification Accuracy
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Verification IP (VIP) & Solutions
What Is Verification IP and Why It Matters in Modern SoC Design
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Design IP & Customization
IP Your Way: Why Customizable IP Is Essential for Modern SoC Design
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Memory & DDR
DDR Verification Challenges in Modern Chip Design
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