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Overview

SmartDV’s USIM Master IP is a silicon-proven, fully featured Universal Subscriber Identity Module interface solution purpose-built for SoC designs requiring reliable, standards-compliant smart card communication across mobile, IoT, automotive, and embedded applications. Fully compliant with ISO/IEC 7816-3 and ETSI TS 102 221 Release 18, it delivers complete USIM master functionality supporting both T=0 and T=1 communication protocols with full smart card session management including card activation, deactivation, cold and warm reset, and ATR response handling — providing a proven, production-ready USIM interface for the most demanding mobile and embedded SoC designs.

Designed for the practical integration requirements of modern mobile and IoT SoC designs, the IP supports adjustable clock and baud rates, configurable automatic byte repetition, Character Waiting Time and Block Waiting Time management, and complete smart card session handling. Its T=0 asynchronous half-duplex character transmission and T=1 asynchronous half-duplex block transmission support give SoC teams a production-tested, spec-complete USIM master implementation that integrates cleanly with the widest range of UICC and smart card devices across 2G, 3G, 4G, and 5G mobile platforms.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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USIM Master
Key Features
  • Full USIM Master Functionality – Complete smart card master implementation per ISO/IEC 7816-3 and ETSI TS 102 221 Release 18 supporting all UICC smart card session functions
  • Complete Smart Card Session Management – Card activation and deactivation, cold and warm reset, and Answer to Reset (ATR) response reception for complete UICC lifecycle management
  • T=0 and T=1 Protocol Support – T=0 asynchronous half-duplex character transmission and T=1 asynchronous half-duplex block transmission for comprehensive smart card protocol coverage
  • Flexible Clock and Baud Rate – Adjustable clock rate and bit rate configuration for adaptation to diverse UICC and smart card device timing requirements
  • Configurable Byte Repetition – Automatic byte repetition support with configurable repetition count for reliable error recovery in noisy smart card communication environments
  • Waiting Time Management – Character Waiting Time (CWT) and Block Waiting Time (BWT) support per ISO/IEC 7816-3 specification for standards-compliant timing management
  • Complete Data Transfer – Full bidirectional data transfer to and from the card for complete APDU command and response handling
Compliance and Compatibility
  • Fully compliant with ISO/IEC 7816-3 specification for smart card electrical interface and transmission protocols
  • Fully compliant with ETSI TS 102 221 Release 18 UICC-Terminal interface specification; backward compatible with earlier releases
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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