SmartDV’s Super IO IP is a silicon-proven, fully integrated Super Input/Output controller solution purpose-built for SoC designs requiring a comprehensive set of legacy and modern peripheral functions in a single, unified IP core. Supporting seven logical devices corresponding to seven individual functions — UART, GPIO, Mailbox, and SWC/ACPI — it delivers a complete Super IO implementation for server, embedded computing, industrial, and automotive SoC designs requiring host-to-SoC messaging, legacy serial communication, power management, and GPIO control within a single integration-ready peripheral controller.
Designed to address the full breadth of Super IO integration requirements, the IP combines a UART 16550-compatible serial controller supporting baud rates from 1800 bps to 3.686 Mbps with a comprehensive GPIO subsystem, a 32-register Mailbox for bidirectional host-to-SoC messaging, and a complete SWC/ACPI power management controller supporting SMI, SCI, SerIRQ, S3/S5 power states, programmable wake-up events, and plug-and-play register sets. Its seven independent logical devices, interrupt controller, configurable FIFOs, and comprehensive status and control registers give SoC teams a production-tested, feature-complete Super IO implementation that eliminates the need for multiple discrete peripheral controllers.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
