SmartDV’s SR-IOV Verification IP is a comprehensive solution for verifying Single Root I/O Virtualization, the PCI-SIG standard enabling a single PCIe physical device to present multiple lightweight, independently assignable virtual devices to virtual machines without hypervisor-mediated I/O emulation. Fully compliant with the PCI-SIG SR-IOV and Sharing Specification Revision 1.1, built on the complete PCIe protocol stack across Gen 1 through Gen 7, it supports complete verification of Physical Function and Virtual Function behavior, the SR-IOV Extended Capability structure including TotalVFs, NumVFs, and VF Enable control, Alternative Routing ID Interpretation (ARI) for extended function addressing, and Access Control Services (ACS) for VF-to-VF isolation, including FLIT mode and PAM4 signaling environments introduced in PCIe 6.0 and 7.0.
SmartDV‘s SR-IOV VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With full underlying PCIe protocol stack verification including LTSSM, encoding, and TLP/DLLP/FLIT handling, comprehensive PF/VF configuration space verification, Address Translation Services integration, automated error injection at all layers, built-in functional coverage, and a complete test suite, SmartDV’s SR-IOV VIP enables verification teams to thoroughly validate SR-IOV capable device designs for cloud and hyperscale NICs, NVMe controllers, GPUs, and any PCIe endpoint requiring multi-tenant virtualized I/O sharing.