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Serial NOR Flash Controller IP

Design IP
Overview

SmartDV’s Serial NOR Flash Controller IP is a silicon-proven, fully featured Serial NOR Flash controller solution purpose-built for SoC designs requiring reliable, high-performance connectivity to Serial NOR Flash devices across embedded, automotive, IoT, and consumer electronics applications. Fully compliant with JEDEC JESD216F and compatible with Serial NOR Flash devices from all major vendors, it delivers complete NOR flash controller functionality supporting Extended I/O, Dual I/O, and Quad I/O protocols in both Single Transfer Rate (STR) and Double Transfer Rate (DTR) modes, with up to 16 slave devices under master control.

Designed to address the full breadth of Serial NOR Flash integration requirements, the IP supports XIP (eXecute In-Place) for direct memory-mapped flash execution, both 3-byte and 4-byte addressing modes for high-density flash devices, 64-bit CRC for data integrity verification, multi-master operation, mode fault detection, and all standard NOR flash commands per specification. Its support for full and half duplex operation, bi-directional mode, programmable clock polarity and phase, flexible clock generation, and configurable FIFO architecture with threshold-based interrupts gives SoC teams a production-tested, spec-complete NOR flash controller that handles the widest range of commercial Serial NOR Flash device configurations.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, LSB and MSB mode support, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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Serial Flash Controller
Benefits
  • Full Serial NOR Flash Controller Functionality – Complete NOR flash controller implementation per JEDEC JESD216F supporting all Serial NOR Flash commands and up to 16 slave devices under master control
  • Multi-Protocol Support – Extended I/O, Dual I/O, and Quad I/O protocols in both STR and DTR modes for flexible NOR flash device coverage
  • Execute-In-Place (XIP) – Direct memory-mapped flash execution support for zero-latency code execution from NOR flash
  • Flexible Addressing – 3-byte and 4-byte addressing modes for access to high-density Serial NOR Flash devices
  • 64-Bit CRC – Hardware 64-bit CRC generation and checking for robust data integrity verification across all flash transactions
  • Multi-Master Operation – Multi-master support with mode fault error flag and CPU interrupt capability for shared bus NOR flash designs
  • Flexible Interface Support – Full duplex, half duplex, and bi-directional operation with programmable clock polarity, phase, LSB/MSB ordering, and flexible serial clock generation
  • Configurable FIFO Architecture – Configurable transmit/receive data FIFOs with threshold-based interrupt generation for efficient flash data transfer management
  • Software and Hardware Reset – Both software and hardware reset support for flexible system initialization
Compliance and Compatibility
  • Fully compliant with JEDEC JESD216F Serial Flash Discoverable Parameters (SFDP) specification
  • Compatible with Serial NOR Flash devices from all major vendors including Infineon, Micron, Macronix, Winbond, and GigaDevice
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

Request Datasheet