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One-Wire Interface Controller IP

Design IP
Overview

SmartDV’s One-Wire Interface Controller IP is a silicon-proven, fully featured single-wire serial communication solution purpose-built for SoC designs requiring reliable, low-cost connectivity to One-Wire peripheral devices such as temperature sensors, memory devices, and iButton security tokens across IoT, automotive, industrial, and embedded applications. Fully compliant with the Dallas/Maxim One-Wire protocol specification, it delivers complete master-side One-Wire functionality over a single data line, enabling power and data delivery to peripheral devices with minimal wiring complexity.

Designed to address the full breadth of One-Wire device management requirements, the IP supports all standard ROM and memory command sequences including Read ROM, Skip ROM, Match ROM, and Search ROM for comprehensive device identification and addressing, alongside Read/Write Memory, Extended Read/Write Memory, and Read/Write Status commands for complete device data management. Its optional glitch suppression capability enhances signal integrity on noisy single-wire bus environments, making it a robust and reliable controller implementation for demanding industrial and automotive applications.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and One-Wire application targets.

One-Wire Interface Controller
Benefits
  • Full One-Wire Master Controller Functionality – Complete master-side implementation of the Dallas/Maxim One-Wire protocol over a single data line supporting both standard and overdrive speed modes
  • Complete ROM Command Support – Read ROM, Skip ROM, Match ROM, and Search ROM commands for comprehensive One-Wire device identification, addressing, and multi-device bus management
  • Complete Memory Command Support – Read Memory, Extended Read Memory, Write Memory, Extended Write Memory, Read Status, and Write Status commands for full One-Wire device data management
  • Multi-Device Bus Support – Unique 64-bit ROM code addressing enabling virtually unlimited One-Wire devices on a single bus via MicroLAN topology
  • Optional Glitch Suppression – Configurable glitch suppression on the single data line for enhanced signal integrity in noisy industrial and automotive environments
  • Single-Wire Implementation – Low-cost, low-complexity single data line interface with optional parasitic power mode support for minimal wiring in space-constrained designs
Compliance and Compatibility
  • Fully compliant with Dallas/Maxim (Analog Devices) One-Wire protocol specification
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows