SmartDV’s OpenGMSL Root IP is a fully featured Gigabit Multimedia Serial Link serializer solution purpose-built for automotive SoC designs requiring reliable, high-bandwidth central compute-side connectivity to edge sensors, cameras, and displays across ADAS, autonomous driving, and in-vehicle infotainment applications. Fully compliant with OpenGMSL v3.0, it delivers complete Root (serializer) functionality supporting forward link data rates up to 12 Gbps and reverse link rates of 187.5 Mbps, with comprehensive support for video streaming, bidirectional sideband data, functional safety, and HDCP content protection, providing a feature-complete OpenGMSL Root implementation for next-generation software-defined vehicle architectures.
As the central compute-side counterpart to the OpenGMSL Leaf deserializer, the Root IP originates video and sensor data streams, distributes them to connected Leaf nodes, and receives reverse link sideband data for bidirectional control and configuration. Its RS-FEC (127,121) encoder for forward link transmission, 9B/10B encoding, scrambling, Reference over Reverse clock reception and synchronization, Precision Time Synchronization, HDCP v1.4 and v2.3 content protection, and functional safety mechanisms give automotive SoC teams a spec-complete, future-ready Root implementation that delivers the reliability and interoperability demanded by next-generation ADAS and autonomous driving zonal compute designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its programmable SERDES interface widths, flexible link topology support, and clean host interface enable fast integration and confident design bring-up across a wide range of automotive process nodes and target applications.
