SmartDV’s MIPI VGI Verification IP is a comprehensive solution for verifying the MIPI Virtual GPIO Interface, a point-to-point full-duplex serial interface designed to consolidate multiple sideband GPIOs and low-speed messaging connections between mobile SoC application processors and peripheral devices over a 2-wire or 3-wire interface. Based on the MIPI VGI draft specification developed by the MIPI Reduced I/O Working Group, it supports complete verification of VGI Host and Peripheral components across 2-wire asynchronous and 3-wire synchronous interface configurations, vGPIO logic-state exchange and messaging exchange communication categories, all three synchronous gear rates, in-band flow control, in-band hard reset, and comprehensive error injection and detection.
SmartDV’s MIPI VGI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With serializer and deserializer support, configurable clock frequencies up to 78 MHz, default 2-wire PWM signaling, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s MIPI VGI VIP enables verification teams to thoroughly validate virtual GPIO interface designs for smartphones, tablets, IoT devices, and mobile-influenced systems requiring pin-count reduction through GPIO and messaging consolidation.