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MIPI SoundWire I3S VIP
Simulation
Overview

SmartDV’s MIPI SoundWire I3S Verification IP is designed to verify the SoundWire I3S interface—an extension of the SoundWire standard for high-performance multichannel audio applications. Fully compliant with the MIPI SoundWire I3S specification, this VIP enables accurate and efficient verification of low-latency, synchronized audio transport between SoCs and external audio components.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with methodologies such as UVM, OVM, and VMM. It is simulator-independent and compatible with all leading EDA vendors’ simulators, providing flexibility across simulation environments.

With configurable master and slave agents, support for frame-based transfers, synchronized channel handling, integrated protocol checkers, and detailed coverage metrics, SmartDV’s MIPI SoundWire I3S VIP empowers verification teams to validate high-bandwidth, multi-channel audio interfaces in mobile, automotive, and professional audio applications.

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MIPI SoundWire I3S VIP
Benefits
  • Comprehensive Verification Environment – Provides full MIPI SoundWire I3S Manager, Peripheral, and Monitor functionality per version 1.1 r02 draft specification.
  • Accurate PHY and Protocol Modeling – Supports PHY 1 (FBCSE 0), PHY 2 (FBCSE 1), and PHY 3 (DLV) modes with NRZS and 8b/10b encoding, FBCSE clock-pause operation, and I/O timing checks.
  • Configurable Manager and Peripheral Behavior – Manager BFM initiates frame transactions based on user-driven commands, while Peripherals synchronize to the bus, process programmed slots, and handle data transfers and error injection via callbacks.
  • Advanced Monitoring and Coverage – The integrated Monitor observes all bus activities, detects protocol and timing violations, tracks access statistics, and implements a comprehensive functional coverage model.
  • Robust Error and Interrupt Verification – Generates and detects Manager and Peripheral errors including CRC, Invalid Packet Length, Opcode, PHY Number, Phase ID, and Row Delay errors, with interrupt handling and event counters for each scenario.
  • Scalable Topology Coverage – Supports up to 12 Peripherals, each with 32 data ports and 16 channels per port, enabling large-scale verification of complex multi-node audio topologies.
  • Customizable Testbench Control – Offers a rich set of APIs and callbacks for user-defined packet generation, event monitoring, and data processing, supported by a complete regression test suite covering all SoundWire I3S specification features.
Compliance and Compatibility
  • Fully compliant with MIPI SoundWire I3S version 1.1 revision 02 draft specification
  • Supports UVM, SystemVerilog, and Verilog for flexible integration into diverse verification flows
  • Compatible with a wide range of simulators, including:
    • Synopsys VCS
    • Cadence Xcelium
    • Siemens Questa
    • Aldec Riviera-PRO
    • Open-Source simulators (e.g., Verilator)

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