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Overview

SmartDV’s MIPI A-PHY Verification IP is a comprehensive solution for verifying the MIPI Automotive Physical Layer SerDes interface, the first standardized automotive long-reach serializer/deserializer specification designed for high-speed, high-reliability point-to-point connectivity between cameras, radar, LiDAR, displays, and electronic control units in ADAS, autonomous driving, and IVI systems. Fully compliant with MIPI A-PHY v2.0 (July 2024) and adopted as IEEE 2977-2021, it supports complete verification of A-PHY source and sink components across single and dual lane configurations, all seven downlink gears from G1 through G7 at data rates from 2 Gbps to 32 Gbps, all three uplink gears from U1 through U3 at rates from 100 Mbps to 1.6 Gbps, both Profile 1 NRZ 8B/10B and Profile 2 PAM4/PAM8/PAM16 physical layer profiles, and the complete APPI interface between A-PHY and native protocols.

SmartDV’s MIPI A-PHY VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive data link layer coverage including BIST, sleep and wakeup, keep-alive, local, multi-port, and network functions, ACMD register and ACMP message support, retransmission mechanisms, re-training sequences, mission mode and unidirectional startup procedures, Power Over A-PHY support, built-in functional coverage, and a complete test suite, SmartDV’s MIPI A-PHY VIP enables verification teams to thoroughly validate automotive SerDes interface designs for ADAS cameras, radar and LiDAR sensors, automotive displays, zonal ECUs, and next-generation in-vehicle network architectures.

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Benefits
  • Full A-PHY Source and Sink Support – Provides complete MIPI A-PHY source and sink component verification across single and dual lane point-to-point serial configurations, supporting the main unidirectional high-speed downlink data stream, bidirectional low-throughput uplink command and control data stream, optional Power Over A-PHY for peripheral power delivery via the A-PHY data line, and the APPI interface between A-PHY and native protocol layers.
  • Comprehensive Downlink and Uplink Gear Coverage – Supports all seven discrete downlink gears including G1 at 2 Gbps, G2 at 4 Gbps, G3 at 8 Gbps, G4 at 12 Gbps, G5 at 16 Gbps, G6 at 24 Gbps, and G7 at 32 Gbps, and all three uplink gears including U1 at 100 Mbps, U2 at 200 Mbps, and U3 at 1.6 Gbps as added in A-PHY v2.0, with reverse downlink support for symmetric configurations.
  • Profile 1 and Profile 2 Physical Layer Support – Supports Profile 1 NRZ 8B/10B encoding for G1 and G2 operation including RTS bypass for uplink and downlink, 8B/10B PCS, and PMD, and Profile 2 PAM4, PAM8, and PAM16 encoding for G1 through G7 including RTS for uplink and downlink, 8B/10B PCS for uplink and reverse downlink, PAM4/8/16 PCS for downlink and reverse downlink, and PMD.
  • A-Packet and Retransmission Support – Supports back-to-back A-packet 8B/10B encapsulation, fully paced A-packet stream, RRS single retransmission, GRS gap retransmission, retransmission request and ACK types, scrambler as per specification, and clock recovery with sink transmitter using recovered source clock for proper port rate generation.
  • ACMD and ACMP Register SupportSupports ACMD registers and ACMP write and read messages in both short and long message formats, covering all defined control and management plane transactions for complete A-PHY link management verification.
  • Startup, Wakeup, and Operating Mode Support – Supports mission mode startup procedure and unidirectional startup procedure, wakeup protocol, and all defined operating modes including Non-Active Mode, Active Mode, and Test Mode, and re-training sequences for link adaptation and maintenance.
  • Data Link Layer Feature CoverageSupports all A-PHY data link layer features including link service covering BIST, sleep and wakeup, and keep-alive, local function, multi-port function, and network function for complete link layer protocol verification.
  • Complete Verification Infrastructure – Provides a full test suite covering all MIPI A-PHY v2.0 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in transmitter and receiver for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with MIPI A-PHY v2.0 (July 2024); backward compatible with A-PHY v1.1 and v1.0
  • Adopted as IEEE 2977-2021 standard
  • Supports all seven downlink gears (G1-G7, 2 Gbps to 32 Gbps) and three uplink gears (U1-U3, 100 Mbps to 1.6 Gbps)
  • Supports Profile 1 (NRZ 8B/10B) and Profile 2 (PAM4, PAM8, PAM16) physical layer profiles
  • Supports MIPI Power Over A-PHY v1.1 (November 2025)
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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