SmartDV’s LPDDR5/5X Verification IP is a comprehensive solution for verifying Low Power Double Data Rate 5 and LPDDR5X memory interfaces across device and PHY interface implementations. Fully compliant with JEDEC JESD209-5C covering both LPDDR5 and the LPDDR5X optional extension and backward compatible with JESD209-5B, JESD209-5A, and JESD209-5, and DFI versions 2.0 through 5.0, it supports complete verification of LPDDR5 and LPDDR5X device components across x8 and x16 device configurations with densities up to 32 GB, covering all defined commands, 2:1 and 4:1 CKR modes, BG, 8B, and 16B bank organization modes, all training modes, refresh management, CA parity, ECC, and the DDR PHY Interface across DDR3, DDR4, DDR5, LPDDR3, LPDDR4, and LPDDR5 memory protocols.
SmartDV’s LPDDR5/5X VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive WCK2CK sync, deep sleep, frequency set point operation, hybrid refresh, refresh credit mode, data copy low power function, write clock free running mode, partial array self-refresh segment masking, DFI multi-protocol support, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s LPDDR5/5X VIP enables verification teams to thoroughly validate LPDDR5 and LPDDR5X memory subsystem designs for flagship smartphones, 5G platforms, automotive ADAS, AR/VR, edge AI, and power-sensitive high-bandwidth computing applications.
