I2S/PDM/TDM VIP

Simulation

Key Features Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s I2S/PDM/TDM Verification IP is a comprehensive solution for verifying the three principal digital audio serial interface protocols used in modern SoC audio subsystems. Compliant with the Philips I2S Bus Specification (1996) for I2S operation and industry-standard implementations for PDM and TDM, it supports complete verification of I2S, PDM, and TDM Transmitter, Receiver, and Controller components, covering up to 32 channels per path, programmable word lengths from 8 to 64 bits, all master and slave operating configurations, PDM modulation and demodulation, and comprehensive error injection and timing violation detection across all three audio interface types.

SmartDV’s I2S/PDM/TDM VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With AT24C1024 EEPROM model support for I2S, PDM modulator and demodulator with digital output and error output, comprehensive TDM multichannel configuration, bus-accurate timing, built-in functional coverage, and complete test suites for all three protocols, SmartDV’s I2S/PDM/TDM VIP enables verification teams to thoroughly validate digital audio interface designs for mobile SoCs, automotive infotainment, smart speakers, professional audio, IoT microphone arrays, and consumer electronics applications.

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Key Features

Full I2S Transmitter, Receiver, and Controller Support – Provides complete I2S Transmitter, Receiver, and Controller functionality with support for up to 32 channels in both transmit and receive paths, programmable word lengths of 8, 12, 16, 20, 24, and 32 bits, programmable padding and bit reversal, left and right justified data formats, programmable data rate on transmit path, and START byte generation and handling.
I2S Master and Slave Configuration Support – Supports all I2S operating configurations including Master or Slave mode as transmitter, Master or Slave mode as receiver, and Master mode as controller without data transmission or reception, with both transmitter and receiver able to work with SCK as input or drive SCK, multi-master arbitration, and clock synchronization.
I2S Transfer and Error Coverage – Covers Start, Repeat Start, and Stop conditions for all possible transfers, Read, Write, General Call, and CBUS transfer types, complex sequences of 7-bit and 10-bit addressing with repeated start, wait state insertion by both Master and Slave, AT24C1024 EEPROM memory model with 256-byte page write mode and random and sequential read modes, and comprehensive error injection including Master abort, ACK on last read, NACK handling, clock period stretching, random write NACK insertion, and glitch injection.
Full PDM Transmitter and Receiver Support – Provides complete PDM Transmitter and Receiver functionality with support for 8, 10, 12, 16, 20, 24, and 32-bit data precision, PDM modulator and PDM demodulator, PDM digital output, and PDM error output for thorough pulse density modulation interface verification.
Full TDM Transmitter, Receiver, and Controller Support – Provides complete TDM Transmitter, Receiver, and Controller functionality with support for up to 32 channels in both transmit and receive paths, programmable word lengths of 8, 12, 16, 20, 24, 32, and 64 bits, programmable padding and bit reversal, left and right justified data formats, and programmable data rate on transmit path.
TDM Master and Slave Configuration Support – Supports all TDM operating configurations including Master or Slave mode as transmitter, Master or Slave mode as receiver, and Master mode as controller without data transmission or reception, with both transmitter and receiver able to work with SCK as input or drive SCK.
Complete Verification Infrastructure – Provides full test suites covering all I2S, PDM, and TDM specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in transmitter, receiver, and monitor for user-defined event handling and protocol and timing violation notification across all three audio interface types.

Compliance and Compatibility

Compliant with Philips I2S Bus Specification (June 5, 1996) for I2S operation
Supports industry-standard PDM and TDM audio interface implementations
Supports programmable word lengths of 8 to 64 bits across I2S, PDM, and TDM
Supports up to 32 channels in transmit and receive paths for I2S and TDM
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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