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Overview

SmartDV’s FlexRay Verification IP is a comprehensive solution for verifying the FlexRay deterministic, fault-tolerant automotive communication protocol, designed for safety-critical applications requiring high-speed, time-triggered and event-triggered network communication. Fully compliant with FlexRay Specification Version 3.0.1 and the corresponding ISO 17458-1 through ISO 17458-5 international standards, it supports complete verification of FlexRay TX and RX node functionality in full duplex operation across all three defined bit rates, covering cluster wakeup and startup, static and dynamic frame generation and reception, and comprehensive syntax and content error injection and detection across all FlexRay protocol layers.

SmartDV’s FlexRay VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With configurable receive FIFO depth, glitch injection and detection, constraints randomization, built-in functional coverage, and a complete test suite, SmartDV’s FlexRay VIP enables verification teams to thoroughly validate FlexRay network interface designs for automotive powertrain, chassis, ADAS, steer-by-wire, brake-by-wire, adaptive cruise control, and other safety-critical in-vehicle communication applications.

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FlexRay VIP
Key Features
  • Full FlexRay TX and RX Node Support – Provides complete FlexRay transmitter and receiver node functionality in full duplex operation, supporting configurable TX and RX operation, all three defined bit rates of 2.5, 5, and 10 Mbit/s, bit alignment, configurable receive FIFO depth, and a rich set of configuration parameters for fine-grain protocol control.
  • Cluster Wakeup and Startup – Supports complete FlexRay cluster wakeup and startup sequences as defined in FlexRay v3.0.1, including all defined startup frame handling, synchronization, and startup frame indicator verification for both single and dual channel configurations.
  • Comprehensive Frame Type Coverage – Supports generation and reception of all FlexRay frame types including static frames for time-triggered deterministic communication in the static segment and dynamic frames for event-triggered communication in the dynamic segment, with complete header, payload, and trailer verification.
  • Comprehensive Syntax Error Injection and Detection – Supports injection and detection of all FlexRay syntax errors including Frame ID errors (Frame ID = 0), Header CRC errors, CRC errors, and oversize and undersize frame errors across all operating bit rates and frame types.
  • Comprehensive Content Error Injection and Detection – Supports injection and detection of all FlexRay content errors including Cycle Count errors, Frame ID errors, Startup/Sync/Null frame errors with respect to the dynamic segment, Startup and Sync frame errors with respect to the static segment, reception of Null frames, and transaction abort conditions.
  • Glitch Injection and Detection – Supports glitch insertion and detection for physical layer fault simulation, enabling verification of FlexRay node behavior under real-world signal integrity conditions and fault tolerance mechanisms.
  • Complete Verification Infrastructure – Provides a full test suite covering all FlexRay v3.0.1 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in TX, RX, and Monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with FlexRay Communications System Protocol Specification Version 3.0.1
  • Compliant with ISO 17458-1 through ISO 17458-5 (FlexRay international standard)
  • Supports all three defined bit rates: 2.5, 5, and 10 Mbit/s
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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